FPGA可编程逻辑器件芯片XC6SLX9-2CPG196I中文规格书

GTX Transmitter (TX)

This chapter shows how to configure and use each of the functional blocks inside the GTX

transmitter.

Transmitter Overview

Each GTX transceiver in the GTX_DUAL tile includes an independent transmitter, which

consists of a PCS and a PMA. Figure6-1 shows the functional blocks of the transmitter.

Parallel data flows from the FPGA into the FPGA TX interface, through the PCS and PMA,

and then out the TX driver as high-speed serial data. Refer to AppendixE, “Low Latency

Design,” for latency information on this block diagram.

9

TX

TX

TX

OOB

Driver

&

Preemp

PCI

Shared

PMA

PLL

Divider

8

7

PISO

4

Polarity

Control

Phase

Adjust

FIFO

Loopback from RX (same channel)

1

2

8B/10B

Encoder

10

3

5

TX

Gearbox

FPGA

TX

Interface

6

TX-PMATX-PCS

PRBS

Generator

TX PIPE Control

From Shared PMA PLL

UG198_c6_01_042407

Figure 6-1:GTX TX Block Diagram

The key elements within the GTX transmitter are:

1.

2.

3.

4.

5.

6.

7.

8.

9.

“FPGA TX Interface,” page 120

“Configurable 8B/10B Encoder,” page 129

“TX Buffering, Phase Alignment, and TX Skew Reduction,” page 141

“TX Polarity Control,” page 147

“TX Gearbox,” page 134

“TX PRBS Generator,” page 148

“Parallel In to Serial Out,” page 149

“Configurable TX Driver,” page 150

“Receive Detect Support for PCI Express Operation,” page 153

10.“TX Out-of-Band/Beacon Signaling,” page 157

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

Chapter 7:GTX Receiver (RX)

In most chip-to-chip applications operating at 5 Gb/s with up to a nominal trace length of

48 inches with approximately 15.5dB of attenuation at 2.5GHz, RX linear equalization

with a slight boost on DFETAP1 is sufficient. TX pre-emphasis can also reduce ISI and

replace the function of DFE.

Table7-9 provides DFETAP1 and RXEQMIX settings for 6.5Gb/s operation for chip-to-

chip applications.

Table 7-9:DFETAP1 and RXEQMIX at 6.5 Gb/s for Chip-to-Chip Applications

DFETAP1

Loss (dB) @ 3.25 GHz

8

11.5

15.5

20

RXEQMIX = 10

10

31

N/A

N/A

RXEQMIX = 00

5

5

25

31

Nominal Trace Length on

FR4 Substrate

(inches [mm])

18 [457.2]

28 [711.2]

38 [965.2]

48 [1219.2]

Notes:

TXDIFFCTRL = 111 and TXPREEMPHASIS = 000 (maximum TX swing and no TX pre-

emphasis).

In most chip-to-chip applications, where the nominal trace length is 10 inches and shorter

at 6.5Gb/s, TX pre-emphasis and continuous time linear equalization are sufficient. For

longer chip-to-chip applications, the DFE should be used.

Example RX Linear Equalizer and DFE Settings for Backplane Applications

Table7-10 provides DFETAP1 and RXEQMIX settings for 4.25Gb/s operation for

backplane applications.

Table 7-10:DFETAP1 and RXEQMIX at 4.25 Gb/s for Backplane Applications

DFETAP1

Loss (dB) @ 2.125 GHz

7.75 - 8.25

9.5 - 11

13.5 - 17

RXEQMIX = 10

5

N/A

N/A

RXEQMIX = 00

0

0

23

Nominal Trace Length on

FR4 Substrate

(inches [mm])

30 [762]

(2)

44 [1117.6]

(3)

64 [1625.6]

(4)

Notes:

TXDIFFCTRL = 111 and TXPREEMPHASIS = 000 (maximum TX swing and no TX pre-

emphasis).

l 30 inches [762mm] trace length = 6 inches [152.4mm] backplane + 2 HmZD or eHSD

connectors (trace length neglected) + 24 inches [609.6 mm] on line cards.

l 44 inches [1117.6 mm] trace length = 20 inches [508 mm] backplane + 2 HmZD or eHSD

connectors (trace length neglected) + 24 inches [609.6 mm] on line cards.

l 64 inches [1625.6mm] trace length = 40 inches [1016mm] backplane+2 HmZD or eHSD

connectors (trace length neglected)

+24 inches [609.6 mm] on line cards.

In most backplane applications operating at 4.25Gb/s with up to a total nominal trace

length of 64inches and an end-to-end attenuation of 17dB at 2.125GHz, RX linear

equalization alone is sufficient.

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

RX OOB/Beacon Signaling

Nominal Trace Length on

FR4 Substrate

(inches [mm])

30 [762]

(2)

44 [1117.6]

(3)

DFETAP1

Loss (dB) @ 2.5 GHz

8.5 - 9.5

11.5 - 13

RXEQMIX = 10

15

-

RXEQMIX = 00

0

5

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

Chapter 7:GTX Receiver (RX)

Table 7-18:RX CDR Attributes (Cont’d)

TypeDescription

This 25-bit attribute allows the operation of the CDR to be adjusted. In

normal operation, set this attribute to its default value.

Attribute

PMA_RX_CFG_0

PMA_RX_CFG_1

25-bit Hex

•

•

•

•

•

For 5x Oversampling operation, set PMA_RX_CFG = 25'0F44000.

For lock-to-reference operation, set PMA_RX_CFG = 25'0F44000.

For synchronous operation, set PMA_RX_CFG = 25'0F44088.

For ±100 PPM operation, set PMA_RX_CFG = 25'0F44088.

For ±1000 PPM operation, set PMA_RX_CFG = 25'0F44089.

RX_EN_IDLE_HOLD_CDR

RX_EN_IDLE_RESET_FR

RX_EN_IDLE_RESET_PH

Notes:

Line Rate in Gb/s.

Boolean

Boolean

Boolean

Enables the CDR to hold data during an optional reset sequence of an

electrical idle state for PCI Express operation.

When TRUE, enables the reset of the CDR frequency circuits during an

optional reset sequence of an electrical idle state for PCI Express operation.

When TRUE, enables the reset of the CDR phase circuits during an optional

reset sequence of an electrical idle state for PCI Express operation.

Description

Before serial data received from the line can be used, the embedded clock in the signal

must be recovered. The CDR circuit in each GTX transceiver is responsible for this

function. It takes a divided, high-speed serial clock from the shared PMA PLL and adjusts

its phase and frequency until its transitions match the incoming data. As shown in

Figure7-7, the result is a clock that matches the clock originally used to generate the serial

stream.

GTX_DUAL

Shared PMA PLL

PLL_RXDIVSEL_OUT

Divide by

{1, 2, 4}

PLL Clock/PLL_RXDIVSEL_OUT

Incoming Serial Data

RX CDR

Circuit

Serial Data

Recovered Serial Clock

UG198_c7_06_123107

Figure 7-7:Conceptual View of RX CDR Circuit

Because transitions in the incoming data are used to recover the serial clock, long runs

without transitions can introduce error.

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

RX Clock Data Recovery

CDR Reset

The CDR must be reset before it can operate on incoming data. There are several ways to

reset the CDR:

•

•

Use the GTXRESET port to reset all components in the GTX_DUAL tile, including the

CDR in each transceiver. See

“Reset,” page 101 for more details.

Use the RXCDRRESET port to reset the CDR block, the OOB circuits for SATA (see

“RX OOB/Beacon Signaling,” page 173), the RX elastic buffer (see “Configurable RX

Elastic Buffer and Phase Alignment,” page 203

), and the remaining sections of the RX

PCS.

Figure7-8 shows the timing of the internal reset signals when RXCDRRESET is asserted.

RXCDRRESET can be asserted asynchronously. When it is asserted, an internal CDR reset

pulse, synchronized to an internally generated 1MHz clock, resets the CDR. Similarly, a

reset pulse is generated for the SATA OOB circuit (internal SATA reset), the RX PCS

datapath (internal RXRESET), and the RX elastic buffer (internal RXBUFRESET). The entire

sequence completes in approximately 5µs.

Asynchronous Pulse

High for at least 2 μs

RXCDRRESET

Internal 1 MHz Clock

Internal CDR Reset

Internal SATA Reset

Internal RXRESET

Internal RXBUFRESET

High for 1 μs

Deasserts 1 μs later

Deasserts 1 μs later

Total Reset time ~ 5 μs

UG196_c7_07_050407

Figure 7-8:Reset Sequence Triggered by RXCDRRESET

Horizontal Sample Point Shift

One advanced feature of the CDR of the GTX transceiver is the built-in horizontal sample

point shift. During normal operation, the CDR finds the transition points in incoming data

and uses them to recover the frequency of the incoming clock.

The transition points are also used to select the optimal time to sample data. To minimize

the chance of error, the CDR attempts to sample data as far from transition points as

possible (that is, at the time when the bit value is most stable). This position is the center of

the data eye (see Figure7-9).

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009